In the prior art, in microcontroller and microprocessor multiplexed buses, address information and data are ordered the same. That is, assuming a memory with 16 bit addressing, with 8-bit data represented as D0:D7, and the 16 bit address represented as A0:A15, the low order address bits and the data bits are multiplexed on a bus as A0/D0, A1/D1, A2/D2 . . . A7/D7. Under this scheme, the high order address bits A8:A15 are connected directly to the memory and the low order address bits are latched by an address latch which captures the data on the bus when an address latch enable (ALE) signal is asserted. As a result, when accesses to consecutive memory locations are required, as is frequently the case, since the low order address bits have changed, in order to properly access the memory, the address must be placed on the address bus meaning the multiplexed data/address bus must have an address placed on it. This multiplexing operation results in reduced performance as compared with operations in which there is no such multiplexing. However, in many applications, cost considerations dictate the use of a microcontroller with such a multiplexing scheme over a microcontroller which does not multiplex the address and data buses, but which is more expensive.